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NXP Semiconductors /MIMXRT1064 /DCP /STAT_CLR

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Interpret as STAT_CLR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0IRQ0READY_CHANNELS0 (None)CUR_CHANNEL 0 (OTP_KEY_READY)OTP_KEY_READY

CUR_CHANNEL=None

Description

DCP status register

Fields

IRQ

Indicates which channels have pending interrupt requests
READY_CHANNELS

Indicates which channels are ready to proceed with a transfer (the active channel is also included)

1 (CH0): CH0

2 (CH1): CH1

4 (CH2): CH2

8 (CH3): CH3
CUR_CHANNEL

Current (active) channel (encoded)

0 (None): None

1 (CH0): CH0

2 (CH1): CH1

3 (CH2): CH2

4 (CH3): CH3
OTP_KEY_READY

When set, it indicates that the OTP key is shifted from the fuse block and is ready for use.

Links

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Register License

Copyright 2016-2019 NXP All rights reserved.

SPDX-License-Identifier: BSD-3-Clause

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data